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Re: NVRAM

Posted: Sun Nov 09, 2014 11:47 pm
by AMDlloydsp
Ahhh... &H400FC180 (The RSID register) bit 3 contains a flag that is set when power voltage falls below the BOD trigger level.

This register is defined in LPC17xx.bas as SCB_RSIR

One could watch that bit with BOD interrupt disabled, then when it becomes set to a "1", enable the interrupts, and see what happens.

I really don't have time to explore that now. Anyone who would, please do.

LLoyd

Re: NVRAM

Posted: Tue Nov 11, 2014 6:01 pm
by AMDlloydsp
Well, DAWM! I just discovered a bug in my code.

The Disable routine below MUST NOT use XOR, unless an enable was done first. Otherwise, XOR sets the bit, rather than clearing it.
It should read thus:

sub BOD_Disable
BOD_ISR = ADDRESSOF Do_Brownout_ISR ' DISable the BOD interrupt.

VICIntEnable AND= (NOT(1<<23)) ' interrupt number of the BOD
endsub

Re: NVRAM

Posted: Wed Nov 12, 2014 2:31 am
by olzeke51
I think your parens are unbalanced, also !!

Re: NVRAM

Posted: Wed Nov 12, 2014 2:39 am
by AMDlloydsp
Yeah... I just typed in the edit here on the forum. So much nicer to have the compiler catch that sort of typo! <G>

Now... back to re-edit.

Lloyd