power down states

Question about power
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YahooArchive
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power down states

Post by YahooArchive »

I have an application where I am using the SuperPro Plus at the beginning of the
process but then need to turn it off so all of the lines are high impedance.
Can the processor do this automatically or do I have to use a pin to trigger a
circuit that pulls power? The line will go to a high impedance state when the
board is off, correct?



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Re: power down states

Post by YahooArchive »

You can make all the lines high impedance.

You can go into low power states, using well under 1 mA, and less than 100
micro-A in some states. But to actually turn off the power supply would require
external circuitry.

If 100 microA is good enough, then check the NXP user manuals for how to do
that.

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Re: power down states

Post by YahooArchive »

nput protection is usually specified with respect to the power rails Vss. e.g.
Vss + 0.3V and thus if the power is off, Vss =0, so a 5.3V maximum suddenly
becomes 0.3V.

With 5V tolerant inputs, specs usually specifify the amount of current the body
diode can handle. So, turning the Super Pro OFF may be a bad thing to do.Â

I did not try to dig through the specs and I'm not sure what your interfacing to
(3.3 or 5V inputs or outputs, but it might make sense to be able to externally
cause the lines to go Hi-Z or essentially use a BUS driver such as a 74HC or HCT
365, 366. The HCT is a 5V part to select the controlling system.

You might also take a look at the MAX300x series of parts.

There are a number of sleep modes for this part. Again, you have to look at he
data sheets.

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Re: power down states

Post by YahooArchive »

I have looked through the NXP user manual extensively and cannot find anything
about turning the pins to a high impedance state. The sleep and power down
modes say that the pin retain there last state.

Sec 4.8.2 (Deep Sleep Mode)
"The processor state and registers, peripheral registers, and internal SRAM
values are preserved throughout Deep Sleep mode and the logic levels of chip
pins remain static."

This would mean the pins retain there last state, correct?


And this section:
Sec 4.8.3 (Power down mode)
"Power-down mode does everything that Deep Sleep mode does, but also turns off
the flash memory."

this section does not address the pin state so I would assume they are static
also, correct?


Finally, this section:
Sec 4.8.4 (Deep Power down mode)
"In Deep Power-down mode, power is shut off to the entire chip with the
exception of the Real-Time Clock, the RESET pin, the WIC, and the RTC backup
registers."

this section does not specifically talk about the pins going to high impedance.
Can I assume they do?

If there is no power to the board at all will the pins go to a high impedance
state?

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Re: power down states

Post by YahooArchive »

> I have looked through the NXP user manual extensively and cannot find anything
about turning the pins to a high impedance state. The sleep and power down
modes say that the pin retain there last state.

When pins are inputs, they are relatively high impedance, but the key is that
the power still has to be applied.

This is true of most all CMOS inputs, there are protection diodes to the GND and
Vss supply so that if the part is powered down, you have a diode from an input
to the turned off supply. Which in most cases it will look like a diode to 0V.

So you need to keep power applied to the chip and then put the chip to sleep.
The open drain pins are the exception, but there are only 2 of those.

> If there is no power to the board at all will the pins go to a high impedance
state?
>

The simple answer is no, and this is true of most any CMOS device, unless it is
specifically designed to handle a powered off state. You will need to keep
power applied and put the CPU to sleep, or to buffer the lines with a powered
device. I don't know of any bidirectional devices that are open-drain (both
ways).

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Re: power down states

Post by YahooArchive »

Thanks. So let me reiterate so I am sure I understand. The pins I want to be
high impedance I turn them into inputs and then put the chip into sleep mode.

If that does not work then I need to add external tristate buffers to the lines.

Can I test the pins with a DMM to determine if they are in a high impedance
state? Would I just read the resistance from pin-to-gnd and pin-to-Vcc and see
if the resistance in high (>Meg)?

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Re: power down states

Post by YahooArchive »

> Thanks. So let me reiterate so I am sure I understand. The pins I want to be
high impedance I turn them into inputs and then put the chip into sleep mode.
>
> If that does not work then I need to add external tristate buffers to the
lines.

Yes that will work, and you do not need external buffers as long as the power is
on the chip and it is in sleep mode.

>
> Can I test the pins with a DMM to determine if they are in a high impedance
state? Would I just read the resistance from pin-to-gnd and pin-to-Vcc and see
if the resistance in high (>Meg)?
>

No, the DMM measures resistance by injecting a voltage into 2 pins and measures
the current. You can't use a meter to make this measurement. There may be
better ways, but one simple method is to use a 1M resistor connected to GND and
then power to see if that pulls the line to that direction, which would tell you
the impedance is in the range of 1M or higher. Make sure your fingers aren't
touching it, because you look like a couple M ohms too.

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Re: power down states

Post by YahooArchive »

Would a level shifter in this series help you?
http://datasheets.maximintegrated.com/e ... AX3012.pdf

They can be bidirectional and tri-stateable.

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Re: power down states

Post by YahooArchive »

Yes I think those chips would work if they are tristate selectable. I already
have some 74LCX541 buffer/line driver chips on my PCB in other areas. If
treating the pins as inputs then going into sleep mode does not work I will use
those.

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